1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor memory device including stacked-gate nonvolatile memory cells having a floating gate and a control gate.
2. Description of the Related Art
A semiconductor device such as a flash memory which is recently used in a memory card or so comprises stacked-gate nonvolatile memory cells with an MOS structure wherein each memory cell has a floating gate and a control gate laminated. In this type of memory cell, data recording or erasure or so-called programming is accomplished as the threshold value of the memory cell is changed by storing charges stored in the floating gate through a tunnel oxide layer directly underlying the floating gate or removing the stored charges. It is known that to execute programming adequately, particularly, to improve the erasure characteristic or reduce the erasure voltage, the capacitor between the floating gate and the control gate should preferably be increased. As one way to achieve it, an attempt has been made to make the opposing areas of those gates larger as much as possible.
However, the layout pitch of memory cells is tended to become smaller to meet a demand of increasing the memory capacity. To make the area of the floating gate larger as much as possible within the restriction of the layout pitch, the interval between the adjoining floating gates should be made narrower. It is however difficult to achieve the narrower interval from the viewpoint of the resolution of the photolithography technology at the time of fabricating the floating gate. Japanese Patent Laid-Open Publication No. 2000-40754 proposes, as a solution to this problem, a technique of forming spacers on both sides of a mask (called hard mask) at the time of fabricating the floating gate by photolithography technology, thereby narrowing the interval between the adjoining hard masks and forming a floating gate pattern using the hard masks.
The technique proposed in Japanese Patent Laid-Open Publication No. 2000-40754 is illustrated in FIGS. 1A to 1C and FIGS. 2A and 2B. Those diagrams are cross-sectional views of a memory cell having an MOS structure in the channel direction. The following discusses the process step by step. First, as shown in FIG. 1A, a device-forming insulating layer 201 is formed on a silicon substrate 200 to define a device forming region, then a tunnel oxide layer 202 is formed at the surface of the silicon substrate 200. Next, a first polysilicon layer 203 for formation of a floating gate, a silicon nitride layer 204 as a protective layer, and a second polysilicon layer 205 as a mask layer are deposited on the entire surface, and a photoresist pattern 206 for formation of a floating gate pattern is formed on the resultant surface. The photoresist pattern 206 reduces the interval between adjoining patterns to a size close to the resolution limit of the photolithography technology.
Next, with the photoresist pattern 206 used as a mask, the second polysilicon layer 205 is selectively etched to form a second polysilicon pattern 205a, the photoresist pattern 206 is removed, then a third polysilicon layer 207 is formed on the entire surface, as shown in FIG. 1B. Then, the third polysilicon layer 207 is subjected to anisotropic dry etching, thus forming a third polysilicon side wall 207a on a side surface of the second polysilicon pattern 205a. Accordingly, a hard mask is formed by the second polysilicon pattern 205a and the third polysilicon side wall 207a and the interval between the adjoining hard masks becomes equal to or smaller than the resolution of the photolithography technology.
Next, as shown in FIG. 1C, using the hard mask comprised of the second polysilicon pattern 205a and the third polysilicon side wall 207a, the protective layer 204 is dry-etched to form a protective layer pattern 204a. 
Subsequently, as shown in FIG. 2A, with the etcher changed, the first polysilicon layer 203 is dry-etched to form a first polysilicon layer pattern 203a. At this time, the second polysilicon pattern 205a and the third polysilicon side wall 207a are removed by the dry etching process, and the first polysilicon layer 203 is etched with the protective layer pattern 204a used as a mask. Therefore, the first polysilicon layer pattern 203a is also patterned to have the interval equal to or smaller than the resolution of the photolithography technology. Next, the protective layer pattern 204a is removed by wet etching.
Thereafter, a capacitance insulating layer 208 is formed on the first polysilicon layer pattern 203a and a fourth polysilicon layer 209 is formed on the capacitance insulating layer 208, as shown in FIG. 2B. A photoresist pattern is formed on the fourth polysilicon layer 209, and the fourth polysilicon layer 209, the capacitance insulating layer 208 and the first polysilicon layer pattern 203a are etched in order using the photoresist pattern 124 as a mask, thereby forming a word line as the control gate with the fourth polysilicon layer 209 and forming a floating gate with the first polysilicon layer pattern 203a, though not illustrated. Further, ions of an N-type impurity are injected into the device forming region by self-alignment using those gates as masks, thereby forming a source region and a drain region. This completes the fabrication of a memory cell.
According to the technique disclosed in Japanese Patent Laid-Open Publication No. 2000-40754, to suitably etch out the protective layer 204 lying over the first polysilicon layer 203 after etching the first polysilicon layer 203, the first polysilicon layer 203 is formed of non-doped polysilicon for the following reason. If doped polysilicon is used to provide the first polysilicon layer 203 with conductivity, the surface of the first polysilicon layer 203 is likely to be damaged at the time of etching the protective layer 204. The non-doped polysilicon is therefore used to prevent such a damage from remaining on the surface of the floating gate. However, the present inventor discovered through studies on the technique that even in case where the first polysilicon layer 203 is formed of non-doped polysilicon, some damage inevitably occurs if the etchant contacts the surface of the first polysilicon layer 203 at the time of etching the protective layer 204. Such a damage produces undulations at the surface of the floating gate fabricated finally, which would greatly affect the uniform thickness of the floating gate. This results in a variation in the amount of charges stored in the floating gate, i.e., a variation in the capacitance of the floating gate in each memory cell, disabling the provision of a semiconductor memory device with an improved erasure characteristic or a reduced erasure voltage.
The use of non-doped polysilicon for the first polysilicon layer 203 requires a process of doping an impurity in the first polysilicon layer 203 after the pattern formation in the process in FIG. 2A, and inevitably increases the number of fabrication processes as compared with the case where the first polysilicon layer 203 is formed of doped polysilicon from the beginning. Further, as the second and third polysilicon layers 205 and 207 are used as a hard mask at the time of forming the pattern of the protective layer 204, part of polysilicon remains as deposition on the surface of the protective layer 204 at the time of etching those polysilicon layers and the remained polysilicon interferes with the subsequent and adequate etching of the protective layer 204. In an extreme case, an unetched part of the protective layer remains on the surface of the fabricated floating gate and becomes a foreign matter at the time of forming the capacitance insulating layer to disable the formation of the uniform and high-quality capacitance insulating layer. The unetched part therefore becomes an obstacle in increasing the capacitance of the capacitor between the control gate and the capacitance insulating layer.